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 Features
* Supply Voltage 5V (Typically) * Very Low Power Consumption: 150 mW (Typically) for -1 dBm Output Level * Very Good Sideband Suppression by Means of Duty Cycle Regeneration of the LO * * * * * *
Input Signal Phase Control Loop for Precise 90 Phase Shifting Power-down Mode Low LO Input Level: -10 dBm (Typically) 50- Single-ended LO and RF Port LO Frequency from 100 MHz to 1 GHz SO16 Package
Benefits
* No External Components Required for Phase Shifting * Adjustment Free, Hence Saves Manufacturing Time * Only Three External Components Necessary, this Results in Cost and Board Space
Saving
1000-MHz Quadrature Modulator U2790B
Electrostatic sensitive device. Observe precautions for handling.
1. Description
The U2790B is a 1000-MHz quadrature modulator using Atmel(R)'s advanced UHF process. It features a frequency range from 100 MHz up to 1000 MHz, low current consumption, and single-ended RF and LO ports. Adjustment-free application makes the direct converter suitable for all digital radio systems up to 1000 MHz, e.g., GSM, ADC, JDC. Figure 1-1. Block Diagram
SPU BBAI BBAI
8 7 6 Power up
PU
1
VS
5,4
LO i Phadj BBBi BBBI
12 15 16 9 10
Duty cycle regenerator
Frequency doubler
0 90
90/control loop
3
RFO
2,11,13,14
GND
4583D-CELL-07/06
2. Pin Configuration
Figure 2-1. Pinning SO16
PU
GND RFO VS VS SPD BBAi BBAi
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
Phadj Phadj GND GND LOi GND BBBi BBBi
Table 2-1.
Pin 1 2, 11, 13, 14 3 4, 5 6 7 8 9 10 12 15, 16
Pin Description
Symbol PU GND RFo VS SPU BBAi BBAi BBBi BBBi LOi Phadj Function Power-up input Ground RF output Supply voltage Settling time power-up Baseband input A Baseband input A inverse Baseband input B Baseband input B inverse LO input Phase adjustment (not necessary for regular applications)
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3. Absolute Maximum Ratings
Parameters Supply voltage Input voltage Junction temperature Storage temperature range Symbol VS Vi Tj TStg Value 6 0 to VS 125 -55 to +125 Unit V V C C
4. Operating Range
Parameters Supply voltage range Ambient temperature range Symbol VS Tamb Value 4.5 to 5.5 -40 to +85 Unit V C
5. Thermal Resistance
Parameters Junction ambient SO16 Symbol RthJA Value 110 Unit K/W
6. Electrical Characteristics
Test conditions (unless otherwise specified): VS = 5V, Tamb = 25C, referred to test circuit, system impedance ZO = 50, fLO = 900 MHz, PLO = -10 dBm, VBBi = 1 Vpp differential.
No.
Parameters Supply voltage range Supply current Baseband Inputs Input-voltage range (differential) Input impedance (single ended) Input-frequency range(5) Internal bias voltage Temperature coefficient
Test Conditions
Pin 4, 5 4, 5 7-8, 9-10
Symbol VS IS
Min. 4.5 24
Typ. 30
Max. 5.5 37
Unit V mA
Type* A A
1.1 1.2 2 2.1 2.2 2.3 2.4 2.5
VBBi ZBBi fBBi VBBb TCBB 0 2.35
1000 3.2
1500
mVpp k
D D D A D
250 2.5 0.1 2.65 <1
MHz V mV/C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. The required LO level is a function of the LO frequency. 2. In reference to an RF output level -1 dBm and I/Q input level of 400 mVpp differential. 3. Sideband suppression is tested without connection at pins 15 and 16. For higher requirements a potentiometer can be connected at these pins. 4. For Tamb = -30C to +85C and VS = 4.5V to 5.5V. 5. By low impedance signal source.
3
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6. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS = 5V, Tamb = 25C, referred to test circuit, system impedance ZO = 50, fLO = 900 MHz, PLO = -10 dBm, VBBi = 1 Vpp differential.
No.
Parameters LO Input Frequency range Input level(1) Input impedance Voltage standing wave ratio Duty cycle range RF Output Output level LO suppression(2) Sideband suppression(2, 3) Phase error(4) Amplitude error Noise floor VSWR 3rd-order baseband harmonic suppression RF harmonic suppression Power-up Mode Supply current
Test Conditions
Pin 12
Symbol fLOi PLOi ZiLO VSWRLO DCRLO
Min. 50 -12
Typ.
Max. 1000
Unit MHz dBm
Type* D D D D D
3 3.1 3.2 3.3 3.4 3.5 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8
-10 50 1.4
-5
2 0.6
0.4 -5 30 32 35 30 -1 35 35 40 35 <1 < 0.25 -132 -144 1.6 35 45
3 fLO = 900 MHz fLO = 150 MHz fLO = 900 MHz fLO = 150 MHz
PRFo LORFo SBSRFo Pe Ae
+2
dBm dB dB deg. dB dBm/Hz
B B B D D D D
VBBi = 2V, VBBi = 3V VBBi = VBBi = 2.5V
NFL VSWRRF SBBH SRFH
2 dB
D
4.9 5 5.1
35
dB
D
VPU 0.5V VPU = 1V CSPU = 100 pF CLO = 100 pF CRFo = 1 nF
4, 5
IPU tsPU
10
1
A
D
5.2 6 6.1 6.2 Notes:
Settling time Switching Voltage Power-on Power-up
6 to 3
10
s
D
1 1
VPUon VPUdown
4 1
V V
D D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. The required LO level is a function of the LO frequency. 2. In reference to an RF output level -1 dBm and I/Q input level of 400 mVpp differential. 3. Sideband suppression is tested without connection at pins 15 and 16. For higher requirements a potentiometer can be connected at these pins. 4. For Tamb = -30C to +85C and VS = 4.5V to 5.5V. 5. By low impedance signal source.
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7. Diagrams
Figure 7-1. Typical Single Sideband Output Spectrum at VS = 4.5V and VS = 5.5V, fLO = 900 MHz, PLO = -10 dBm, VBBI = 1 VPP (differential) Tamb = 25C
Figure 7-2.
Typical GMSK Output Spectrum
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Figure 7-3.
Demo Board Layout
Figure 7-4.
OIP3 versus Tamb, LO = 150 MHz, Level -20 dBm
16
12
IP3 (dBm)
VBBI = 0.2 VPP
8
VBBi= 0.4 VPP
4
0 -40 -20 0 20 40 60
80 100 Temperature (C)
6
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Figure 7-5. OIP3 versus Tamb, LO = 900 MHz, Level -10 dBm
12 10
VBBi = 0.4 VPP
IP3 (dBm)
8 6
VBBi = 1.0 VPP
4 2 0 -40 -20 0 20 40 60 80 100 Temperature (C)
Figure 7-6.
Output Power versus Tamb
0.5 0
Output Power (dBm)
-0,5 -1 -1.5 -2 -2.5 -40 -20 0 20
FLO = 150 MHz
FLO = 900 MHz
40
60
80
100
Temperature (C)
Figure 7-7.
Supply Current versus Tamb
40
Supply Current (mA)
30
20
10
0 -40 -20 0 20 40 60 80 100 Temperature (C)
7
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Figure 7-8.
Typical S11 Frequency Response of the RF Output
Figure 7-9.
Typical VSWR Frequency Response of the RF Output
8
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Figure 7-10. Typical S11 Frequency Response of the LO Input
Figure 7-11. Typical VSWR Frequency Response of the LO input
10
8
VSWR
6
4
2
0 100 LO Frequency (MHz) 1000
9
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Figure 7-12. Typical Supply Current versus Temperature at VS = 5V
60
Supply Current ( mA )
50
40
30
20
10 -40 -20 0 20 40 60 80 100 Temperature (C)
Figure 7-13. Typical Output Power versus LO-Frequency at Tamb = 25C, VBBI = 230 mVPP (differential)
0
Output Power ( dBm )
-5
0
200
400
600
800
1000 1200 1400
LO Frequency ( MHz )
Figure 7-14. Typical required VBBi Input Signal (differential) versus LO Frequency for PO = 0 dBm and PO = -2 dBm
2
VBBi (differential) (VPP)
1
0 0 200 400 600 800 1000 1200 1400 LO Frequency (MHz)
10
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U2790B
Figure 7-15. Typical useful LO Power Range versus LO Frequency at Tamb = 25 C
0
-10
LO Power (dBm)
-20
-30
-40
-50 0 200 400 600 800 1000 1200 1400 LO Frequency (MHz)
Figure 7-16. Application Circuit
CPU A inv 220n
8 6 1
SPU
PU 1n
Power down
A
220n BBAi BBAi
7
Power down 5,4
VS 1n
VS 100n
Baseband LO processing VS B
100p 10k LOi Phadj BBBi BBBi 220n
12 15 16 9 10
Duty cycle regenerator
Frequency doubler
0 90
90/ control loop
3
OUT RFO
220n
2,11,13,14
Binv
GND
11
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Figure 7-17. Demo Board Layout
12
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8. Application Notes
8.1 Noise Floor and Settling Time
In order to reduce noise on the power-up control input and improve the wide-off noise floor of the 900-MHz RF output signal, capacitor CPU should be connected from pin 6 to ground in the shortest possible way. The settling time has to be considered for the system under design. For GSM applications, a value of CPU = 1 nF defines a settling time, tsPU, equal or less than 3 ms. This capacitance does not have any influence on the noise floor within the relevant GSM mask. For mobile applications the mask requirements can be achieved very easily without CPU. A significant improvement of the wide-off noise floor is obtainable with CPU greater than 100 nF. Such values are recommended for applications where the settling time is not critical such as in base stations. Coupling capacitors for LOi and RFO also have a certain impact on the settling time. The values used for the measurements are CLOi = 100 pF and CRFo = 1 nF.
8.2
Baseband Coupling
The U2790B-FP (SO16) has an integrated biasing network which allows AC coupling of the baseband signal at a low count of external components. The bias voltage is 2.5V 0.15V. Figure 7-17 shows the baseband input circuitry with a resistance of 3.2 k for each asymmetric input. The internal DC offset between A and A, and B and B is typically < 1 mV with a maximum of 3 mV. DC coupling is also possible with an external DC voltage of 2.5 0.15V. Figure 8-1. Baseband Input Circuitry
Mixer input stage 3.2 k
A
,
B
A
,
B
13
4583D-CELL-07/06
RF Output Circuitry LO Input Circuitry
VS RFO 20 3
Figure 8-2.
LO Input Circuitry
LO 12 50 20 pF
14
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9. Ordering Information
Extended Type Number U2790B-NFPH U2790B-NFPG3H Package SO16 SO16 Remarks Tube, Pb-free Taped and reeled, Pb-free
10. Package Information
Package SO16
Dimensions in mm
10.0 9.85 5.2 4.8 3.7
1.4 0.4 1.27 8.89 16 9 0.25 0.10 0.2 3.8 6.15 5.85
technical drawings according to DIN specifications
1
8
11. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4583D-CELL-07/06 History * Page 3, Abs. Max.Ratings table: Storage temperature values changed * Page 2, Pin Description table: symbol of Pins 8 and 10 changed * Put datasheet in a new template
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4583D-CELL-07/06
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4583D-CELL-07/06


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